Digital computers are used in many applications, including banking, industrial control processes, and other business systems. The digital computer is also used for controlling vehicles, such as aircraft, spacecraft, boats, and land vehicles. For example, automatic flight control systems for commercial and military aircraft use digital computers. In many applications, computations performed by these digital computers need to be performed in substantially “real time.”
Digital computers may include numerous discrete semiconductor or integrated circuit bi-stable elements, generally referred to as latches. A latch is an electronic device that can switch between two stable states in response to low amplitude, high speed signals. Latches are utilized to construct much of the internal hardware of a digital computer, such as logic arrays, memories, registers, control circuits, counters, arithmetic and logic units, and so on.
Digital computers are subject to disturbances that may upset the digital circuitry, but not cause permanent physical damage. For instance, digital computers may operate at nanosecond and sub-nanosecond speeds causing rapidly changing electronic signals to flow through the computer circuits. These signals may generate electromagnetic fields, which may couple to circuits in the vicinity of the signals. While these signals can set latches into desired states, they can also set latches into undesired states. An erroneously set latch can compromise the data processed by the computer and, possibly, completely disrupt the data processing flow of the computer. In digital computer based systems, an error mode that does not result from component damage is typically referred to as a digital system upset or a soft fault.
Digital system upset can also result from spurious electromagnetic signals, such as those caused by lightning, which, for example, can be induced onto the internal electrical cables throughout an aircraft. Such transient signals can propagate to internal digital circuitry, setting latches into erroneous states. These transient signals represent a certain amount of energy. The changing state of the latch in this case is the result of a transfer of energy from the lightning induced transient signal to the electrical circuitry of the latch.
In addition to the energy transfer possible with a signal induced by a lightning event, other events can also provide enough energy transfer to change a latch state. For example, the intense fields associated with electromagnetic weapons, such as electromagnetic pulse (EMP) from a nuclear weapon detonation, high power microwave (HPM), or high-energy nuclear/atomic particles (from a variety of sources, e.g., atmospheric neutrons, cosmic radiation, nuclear weapon detonation, etc.), may deposit sufficient energy into bulk semiconductor material of the digital devices to set latches in erroneous states. Static discharges, power surge switching transients, and radar pulses may also produce spurious signals that can induce electrical transients on system lines and data buses, which in turn can propagate to internal digital circuitry, setting latches in erroneous states.
As described above, the nature of the events that can provide enough energy to change a latch state can be deterministic or stochastic. A latch change into an erroneous state due to such events is referred to as an event upset.
When unintended logic state changes occur, the system may not operate as intended. Energy from an event upset may compromise the data stored within the random access memory (RAM) area of the computer. A digital computer is susceptible to complete disruption if an incorrect result is stored in any of the memory elements associated with the digital computer. Safety-critical digital avionic computer applications, such as fly-by-wire or auto-pilot landings, cannot tolerate digital system upset due to event upsets. These safety-critical digital computers need to be designed to tolerate such event upsets without affecting the performance of the critical application.
One method to reduce the impact of event upsets on a digital computer is described in U.S. Pat. No. 6,163,480, which is assigned to the same assignee as the present application. The memory system for the digital computer includes a backup memory that includes hardened memory cells. Data that is critical for the dynamic restoration of the digital computer and to the operational state/status of the digital computer prior to the occurrence of a soft fault is stored in the backup memory. After an event upset, the digital computer can retrieve this data from the backup memory, which is not impacted by the event upset. Thus, the digital computer is restored to its operational state prior to the occurrence of the soft fault.
However, the backup memory typically has a write time that is slower than that of the main memory. Thus, an interface is needed between the main memory and the backup memory. Because computations within the digital computer for some applications need to be performed in substantially real time, it would be beneficial to provide an interface that allows critical data to be written to the backup memory without impacting the operation of the digital computer.